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november 2015 docid028134 rev 2 1 / 13 this is information on a product in full production. www.st.com STL11N6F7 n - channel 60 v, 10 m typ., 11 a stripfet? f7 power mosfet in a powerflat? 3.3x3.3 package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d STL11N6F7 60 v 12 m 11 a features ? among the lowest r ds(on) on the market ? excellent figure of merit (fom) ? low c rss /c iss ratio for emi immunity ? high avalanche ruggedness applications ? switching applications description this n - channel power mosfet utilizes stripfet? f7 t echnology with an enhanced trench gate structure that results in very low on - state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. table 1: device summary order code marking package packing STL11N6F7 11n6f powerflat? 3.3x3.3 tape and reel d(5, 6, 7, 8) g(4) s(1, 2, 3) 8 1 2 3 4 7 6 5 am15810v1 1 2 3 4 powerfl a t? 3.3x3.3
contents STL11N6F7 2 / 13 docid028134 rev 2 contents 1 electrical ratings ................................ ................................ ............... 3 2 electrical characteristics ................................ ................................ . 4 2.1 electrical characteristics (curve) ................................ ........................ 5 3 test circ uits ................................ ................................ ...................... 7 4 package mechanical data ................................ ................................ 8 4.1 powerflat 3.3x3.3 package information ................................ ......... 9 5 revision history ................................ ................................ .............. 12
STL11N6F7 electrical ratings docid028134 rev 2 3 / 13 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v ds drain - sourc e voltage 60 v v gs gate source voltage 20 v i d (1) drain current (continuous) at t c = 25 c 47 a drain current (continuous) at t c = 100 c 30 i dm (1) (2) drain current (pulsed) 188 a i d (3) drain current (continuous) at t pcb = 25 c 11 a drain current (continuous) at t pcb = 100 c 7 i dm (2) (3) drain current (pulsed) 44 a p tot (1) total dissipation at t c = 25 c 48 w p tot (3) total dissipation at t pcb = 25 c 2.9 w t j operating junction temperature - 55 to 150 c t stg storage tempera ture notes: (1) this value is rated according to r thj - c (2) pulse width limited by safe operating area (3) this value is rated according to r thj - pcb table 3: thermal data symbol parameter value unit r thj - pcb (1) thermal resistance junction - pcb max 42.8 c/w r thj - case thermal resistance junction - case max 2.6 c/w notes: (1) when mounted on fr - 4 board of 1 inch2, 2oz cu, t < 10 sec
electrical characteristics STL11N6F7 4 / 13 docid028134 rev 2 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4: static symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage i d = 1ma, v gs = 0 v 60 v i dss zero gate voltage drain current v gs = 0 v , v ds =60 v 1 a i gss gate - body leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2 4 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 5.5 a 10 12 m table 5: dynamic symbol parameter t est conditions min. typ. max. unit c iss input capacitance v ds = 30 v, f = 1 mhz,v gs = 0 v - 1035 - pf c oss output capacitance - 450 - pf c rss reverse transfer capacitance - 53 - pf q g total gate charge v dd = 30 v, i d = 11 a, v gs = 10 v (see figure 14: "test circuit for gate charge behavior" ) - 17 - nc q gs gate - source charge - 5.7 - nc q gd gate - drain charge - 5.7 - nc table 6: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on del ay time v dd = 30 v, i d = 5.5 a, r g = 4.7 , v gs = 10 v (see figure 13: "test circuit for resistive load switching times" ) - 14.5 - ns t r rise time - 15.3 - ns t d(off) turn - off delay time - 19.4 - ns t f fall time - 8 - ns table 7: source - drain diode symbol parameter test conditions min. typ. max. unit v sd (1) forward on voltage i sd = 11 a, v gs = 0 v - 1.2 v t rr reverse recovery time i d = 11 a, di/dt = 100 a/s v dd = 48 v (see figure 15: "test circuit for inductive load switching and diode recovery times" ) - 26.8 ns q rr reverse recovery charge - 14.2 nc i rrm reverse recovery current - 1.06 a notes:
STL11N6F7 electrical characteristics docid028134 rev 2 5 / 13 (1) pulsed: pulse duration = 300 s, duty cyc le 1.5% 2.1 electrical characteristics (curve) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistanc e
electrical characteristics STL11N6F7 6 / 13 docid028134 rev 2 figure 8 : capacitance variations figure 9 : normalized gate threshold voltage vs temperature figure 10 : normalized on - resistance vs temperature figure 11 : normalized v(br)dss vs temperature figure 12 : source - drain diode forward characteristics
STL11N6F7 test circuits docid028134 rev 2 7 / 13 3 test circuits figure 13 : test circuit for resistive load switching times figure 14 : test circuit for gate charge behavior figure 15 : test circuit for inductive load switching and diode recovery times figure 16 : unclamped inductive load test circuit figure 17 : unclamped inductive waveform figure 18 : switching time waveform
package information STL11N6F7 8 / 13 docid028134 rev 2 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definit ions and product status are available at: www.st.com . ecopack ? is an st trademark.
STL11N6F7 package information docid028134 rev 2 9 / 13 4.1 powerflat 3.3x3.3 package information figure 19 : powerflat? 3.3x3.3 pa ckage outline bot t om view side view t o p view 8465286_ a
package information STL11N6F7 10 / 13 docid028134 rev 2 table 8: powerflat? 3.3x3.3 package mechanical data dim. mm min. typ. max. a 0.70 0.80 0.90 b 0.25 0.30 0.39 c 0.14 0.15 0.20 d 3.10 3.30 3.50 d1 3.05 3.15 3.25 d2 2.15 2.25 2.35 e 0.55 0.65 0.75 e 3.10 3.30 3.50 e1 2.90 3.00 3. 10 e2 1.60 1.70 1.80 h 0.25 0.40 0.55 k 0.65 0.75 0.85 l 030 0.45 0.60 l1 0.05 0.15 0.25 l2 0.15 8 10 12
STL11N6F7 package information docid028134 rev 2 11 / 13 figure 20 : powerflat? 3.3x3.3 recommended footprint 8465286_footprint
rev ision history STL11N6F7 12 / 13 docid028134 rev 2 5 revision history table 9: document revision history date revisi on changes 21 - jul - 2015 1 first release. 17 - nov - 2015 2 document status changed from preliminary to production data. updated title and features in cover page updated table 2: "absolute maximum ratings" and section 4: "electrical characteristics" . added section 4.1: "electrical characteristics (curve)" . minor text changes
STL11N6F7 docid028134 rev 2 13 / 13 important notice C pl ease read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtai n the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and us e of st products and st assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different f rom the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersede s and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics C all rights reserved

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